This invention relates to a semiconductor memory device and, in particularly, to a semiconductor memory device including nonvolatile memory elements.
In resent year, a semiconductor memory device is made on a large scale every year. For example, in a Dynamic Random Access Memory (which is abbreviated as DRAM), a product having a memory capacity of 1 gigabits is developed and goes into actual use. In a large-capacity semiconductor memory device, it is difficult to perfectly exclude defects in some of memory cells during manufacturing the large-capacity semiconductor memory device. For this purpose, the large-capacity semiconductor memory device comprises redundancy circuits for replacing the defective memory cells by redundant memory cells to remedy the defective memory cells. More specifically, the redundancy circuits give relief to the defective memory cells by storing addresses for the defective memory cells in nonvolatile memory elements and by substituting the redundancy or spare memory cells for the defective memory cells. By giving relief to the defective memory cell by the redundancy circuits, yields of the large-capacity semiconductor memory device are improved and the costs thereof is cut down.
The nonvolatile memory elements comprise, for example, fuse elements which are fused a poly-silicon wires or metal wires by a laser beam or a large current, and anti-fuse elements which are applied with a high voltage higher than a critical voltage to be short-circuited. The anti-fuse elements are called AF elements. In recent times, the AF elements are adopted in many instances. This is because it is possible to write information in a process after assembling of a package, a consumed power is small so that the current for breaking down the dielectric film is considerable smaller than the current for fusing the wires, and so on. In the manner which is described above, the semiconductor memory device including the AF elements is commonly used.
The description will proceed to the anti-fuse element acting as the nonvolatile memory element. The anti-fuse element comprises a capacitance element where an insulating film sandwiched between both electrodes. By breaking-down the capacitance element, a write-in (a programming) of a memory data is carried out. The semiconductor memory device comprises a write-in circuit (a programming circuit) therein. The write-in circuit (the programming circuit) applies a high voltage between the both electrodes of the capacitance element to break down the insulating film of the capacitance element and thereby to short the both electrodes. By breaking down the insulating film of the capacitance element to make resistance of the capacitance element low, information is programmed in the memory element. Programming for the anti-fuse element enables after packaging of the semiconductor memory device and one of features of the anti-fuse element is that it is possible to write information in any process.
Therefore, the write-in circuit (the programming circuit) comprises a high voltage generating circuit for generating a high voltage which is adequate for braking down the capacitance element. As the high voltage generating circuit, a pumping circuit for pumping a supplied power supply voltage is used. The high voltage for breaking down the capacitance element is obtained by multiplying the power supply by a factor of several by the pumping circuit. In this event, as the power supply voltage, a voltage as high as possible is supplied in order to make stages of pumping few and to make the efficiency of the current improve. Therefore, as the power supply voltage, a maximum rated voltage value of an operation power supply voltage, an absolute maximum rated voltage value thereof, or a screening voltage value is used. The screening voltage is for detecting an initial defect and is higher than the absolute maximum rated voltage.
The uses of the anti-fuse elements are multifaceted. For example, the anti-fuse elements are used not only in a replacement of the defective addresses in the above-mentioned redundancy circuits but also timing adjustment to a delay circuit, control of an internal circuit, changing of word (bit, word) configuration in a memory device, or the like.
FIG. 9 shows a process flow related to programming of the anti-fuse elements in the semiconductor memory device. The process for programming the anti-fuse elements is carried out in a wafer test T1 in a wafer state and a packaging test T2 at evaluation and screening after assembling a product. In the wafer test T1, programming is largely carried out for anti-fuse elements for switching an internal operation. In addition, in the packaging test T2, programming is carried out for not only the anti-fuse elements for switching the internal operation but also anti-fuse elements for replacing defective addresses. A normal semiconductor memory device is shipped to a user after the packaging test T2 has completed.
However, in recent years, miniaturization of the semiconductor memory devices is required and semiconductor makers largely ship the semiconductor memory devices after assembling the semiconductor memory devices into a module or PoP (Package on Package). Under the circumstances, a module (PoP) test T3 after assembling the module or PoP is added as shown in a right hand of FIG. 9. Inasmuch as defects occur caused by addition of assembling the module or PoP, replacement of the defective addresses for the redundancy circuit from the defective memory cells is carried out.
However, the semiconductor devices mounted on the module are not always have the same withstand voltage for the power supply voltage. In other words, the semiconductor memory devices having low withstand voltages for the power supply voltage are mounted in the module although the semiconductor memory devices are enable to operate at the same power supply voltage. Under the circumstance, when the module is supplied with the power supply voltage used in a step-up circuit for destroying conventional anti-fuse elements, the semiconductor memory devices having the low withstand voltage for the power supply voltage might destroy. On the other hand, when the supplied power supply voltage is lowered, a desired high voltage cannot be obtained and it is impossible to program the anti-fuse elements because the anti-fuse elements cannot be destroyed. Accordingly, in the module where the semiconductor memory devices having the high withstand voltage for the power supply voltage and the semiconductor memory devices having the low withstand voltage for the power supply voltage are mixed and mounted thereon, the problem that the anti-fuse elements cannot be used are just beginning to come to the surface. Inasmuch as the redundancy circuits using the anti-fuse elements cannot be used, the conventional semiconductor memory device is disadvantageous in that yields of the module are reduced and the cost of the module is increased.
A prior art in relation to the anti-fuse elements is already known, for example, in a patent document 1 (Japanese Unexamined Patent Application Publication of Tokkai No. 2004-022,736 or JP-A 2002-22736 which corresponds to U.S. Pat. No. 6,759,895). The patent document 1 describes a data latch circuit having anti-fuse elements. The data latch circuit comprises a voltage selection block, first and second p-channel MOSFETs constituting a latching block, first and second n-channel MOSFETs for setting programming data, and third and fourth n-channel MOSFETs constituting capacitive anti-fuse elements to be programmed with a logic level “1” or “0”. The third n-channel MOSFET is called a first anti-fuse element while the fourth n-channel MOSFET is called a second anti-fuse element. The logic level “1” to be stored in the data latch circuit effects dielectric breakdown of the gate insulation film of the second anti-fuse element, whereas logic level “0” effects dielectric breakdown of the gate insulation film of the first anti-fuse element. The voltage selection block is connected to a first power source providing a normal operating voltage and a second power source providing a programming voltage. The voltage selection block selects one of the normal operating voltage and programming voltage based on a pair of programming control signals, thereby delivering a selected voltage through a voltage selection node. The first and the second anti-fuse elements may comprise third and fourth p-channel MOSFETs having gates connected to the ground. The gates of the third and forth p-channel MOSFETs may be connected to a third power source having a negative potential instead of the ground. This configuration can reduce the programming voltage by a voltage corresponding to the negative potential.
In addition, a patent document 2 (Japanese Patent No. 3,660,828 which corresponds to U.S. Pat. No. 6,114,247) discloses an anti-fuse programming circuit using a variable voltage generator. The variable voltage generator includes a switching part for switching an output signal from the variable voltage generator to any one of a source voltage and a half voltage in response to a programming signal and complementary programming signal.
However, the above-mentioned prior art patent documents 1 and 2 neither describe nor understand a problem related to different withstand voltages of power supply voltage for the semiconductor devices in the module. Accordingly, inasmuch as the problem is not understood, the above-mentioned prior art patent documents 1 and 2 never teach technique for resolving the problem. Therefore, the above-mentioned prior patent documents 1 and 2 are disadvantageous in that it is impossible to use a redundancy circuit in the module.